sd-14620 series two-channel synchro/resolver-to- digital converters description the sd-14620 series converters are small, low-cost, two-channel hybrid synchro- or resolver-to-digital con- verters based on a single-chip mono- lithic. the sd-14620xs option offers synthesized reference circuitry to cor- rect for phase shifts between the ref- erence and signal inputs. the two channels are independent but share the digital output and +5 vdc power pins. the package is 54-pin ceramic, yet is the size of a 28-pin ddip. resolution programming allows selection of 10-, 12-, 14- or 16-bit modes. this feature allows selection of either low-resolution for fast track- ing or higher resolution for higher accuracy. the velocity outputs (vel a, vel b) of the sd-14620 series, which can be used to replace a tachometer, are 4 v signals referenced to analog ground. the sd-14620 series also offers built-in-test outputs for each channel (bit -a, bit -b). the converters are available with operating temperature ranges of 0c to +70c, -40c to +85c and -55c to +125c. mil- prf-38534 processing is available. applications with its low-cost, small size, high accuracy and versatile performance, the sd-14620 series converters are ideal for use in modern high-perfor- mance military, commercial and space position control systems. typical appli- cations include radar antenna posi- tioning, motor control, robotics, navi- gation and fire control systems. features ? synthesized reference option ? 1 minute accuracy available (?s? option only) single +5 v power supply 10-, 12-, 14- or 16-bit programmable resolution small 54-pin ceramic package bit output velocity output replaces tachometer high reliability single chip monolithic -55c to +125c operating temperature range mil-prf-38534 processing available s1 s2 s3 input option control transformer gain demodulator rh rl r i c i vel integrator hysteresis vco & timing 14/16 bit up/down counter data latches em data el inh s4 bit detector reference conditioner error bit r los b cb 8 8 dc-dc converter filter 47 f external capacitor +5 v +5 v -5 v a b a "s" option synthesized reference ? 1991, 1999 data device corporation figure 1. sd-14620 block diagram (one channel) available as radiation hardened in rad-pak? technology by space electronics inc. new
2 table 1. sd-14620 series specifications (each channel) these specs apply over the rated power supply, temperature, and refer- ence frequency ranges; 10% signal amplitude variation, and 10% har- monic distortion. parameter unit value resolution bits programmable 10, 12, 14, or 16 accuracy min 1, 2 or 4, + 1 lsb (see table 5) repeatability lsb 1 max. reference input type differential linearity lsb (rh, rl) each channel differential 1 max. sd-14620 voltage range frequency input impedance single ended differential common-mode range sd-14620xs voltage range frequency input impedance single ended differential common-mode range sig/ref phase shift vrms hz ohm ohm vpeak vrms hz ohm ohm vpeak deg. 2 & 11.8 v units 2-35 360 - 5k 60k 120k 50, 100 transient 2-35 1k - 5k 40k 80k 50, 100 transient 45 max 90 v unit 10-130 60 (47-5k) 400 (360-5k) 270k min. 540k min. 200, 300 transient ? ? ? ? ? ? signal input characteristics 90 v synchro input (l-l) zin line-to-line zin line-to-ground common-mode voltage 11.8 v synchro input (l-l) zin line-to-line zin line-to-ground common-mode voltage 11.8 v resolver input (l-l) zin line-to-line zin line-to-ground common-mode voltage 2 v direct input (l-l) voltage range max. voltage w/o damage input impedance 2 v resolver input (l-l) zin single ended zin differential common-mode voltage ohm ohm v ohm ohm v ohm ohm v vrms v ohm ohm ohm v 123k 80k 180 max. 52k 34k 30 max. (same for ? s ? option) 140k 70k 30 max. 2 nom, 2.3 max. 25 cont, 100 pk transient 20 m || 10 pf min. ( ? s ? option only) 11k 22k 4.9 max. table 1. sd-14620 series specifications (continued) parameter unit value digital input/output inputs (continued) each channel resolution control inhibit (lnh ) (common) enable bits 1 to 8 (em ) enable bits 9 to 16 (el ) outputs parallel data each channel built-in-test drive capability bits ttl cmos each channel see table 2. logic 0 inhibits; data stable within 0.5 s logic 0 enables; data stable within 150 ns logic 1 = high impedance data high z within 100 ns common to all channels 16 parallel lines; 2 bytes nat- ural binary angle, positive logic. (see table 3) each channel logic 0 = bit condition. ~ 100 lsbs of error with a filter of 500 s for los. (los and lor for ? s ? option) 50 pf + logic 0; 1 ttl load, 1.6 ma at 0.4 v max logic 1; 10 ttl loads, -0.4 ma at 2.8 v min logic 0; 100mv max. logic 1; +5 v supply minus 100 mv min. velocity characteristics (see note 1) polarity voltage range (full scale) scale factor scale factor tc reversal error linearity linearity (90 v/60 hz) zero offset zero offset tc load noise v % ppm/ c % % % mv v/ c kohm (vp/v)% each channel positive for increasing angle 4.0 typ. 3.5 min. 10 typ. 20 max. 100 typ. 200 max. 1 typ. 2 max. 0.5 typ. 1 max. 2 typ. 3 max. 5 typ. 10 max. 15 typ. 30 max. 20 max. 0.125 min. 2 max. 1 typ. power supplies nominal voltage voltage tolerance max. voltage w/o damage current v % v ma +5 5 +7 60 typ. 70 max. dc error (e) v -1.25 per +1 lsb error filtered (3 lsb range). temperature range operating -30x -20x -10x storage c c c c 0 to +70 -40 to +85 -55 to +125 -65 to +150 physical characteristics size weight 1.50 x 0.78 x 0.21 (36.75 x 19.81 x 5.33) 0.66 (18.71) in (mm) oz (g) digital input/output logic type inputs ttl/cmos compatible logic 0 = 0.8 v max. logic 1 = 2.0 v min. loading (per channel) =10 a max p.u. current source to +5 v || 5 pf max. cmos transient protected. notes: 1. refer to table 4 for full-scale tracking rate.
3 table 2. resolution control (a and b) resolution b a 10 bit 0 0 12 bit 0 1 14 bit 1 0 16 bit 1 1 theory of operation the sd-14620 series of converters are based upon a single chip cmos custom monolithic. using the latest technology, precision analog circuitry is merged with digital logic to form a complete, high-performance tracking synchro/resolver-to-digital (s/d, r/d) converter. converter operation figure 1 is the functional block diagram of the sd-14620 series. the converter operates with a single +5 vdc power sup- ply and each channel internally generates a negative voltage of approximately 5 volts. these negative voltages are connected to pin 52 (channel ? a ? filter point) and pin 24 (channel ? b ? filter point) ? see general setup considerations. the converter is made up of three main sections; an input front- end, an error processor, and a digital interface. the converter front-end differs for synchro, resolver and direct inputs. an elec- tronic scott-t is used for synchro inputs, a resolver conditioner for resolver inputs, and a sine and cosine voltage follower for direct inputs. these amplifiers feed the high accuracy control transformer (ct). its other input is the 16-bit digital angle . its output is an analog error angle, or difference angle, between the two inputs. the ct performs the ratiometric trigonometric com- putation of sin cos - cos sin = sin( - ) using amplifiers, switches, logic, and capacitors in precision ratios. the converter accuracy is limited by the precision of the computing elements in the ct. ratioed capacitors are used in the ct in these convert- ers, instead of the more conventional precision ratioed resistors. capacitors that are used as computing elements with op-amps are sampled at a high rate to eliminate drift and the op-amp off- sets. the error processing is performed using the industry standard technique for type ii tracking r/d converters. the dc error is integrated yielding a velocity voltage which in turn drives a volt- age- controlled oscillator (vco). this vco is an incremental inte- grator (constant-voltage input to position-rate output) that, together with the velocity integrator, forms a type ii servo feed- back loop. a lead in the frequency response is introduced to sta- bilize the loop and a lag at a higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. general set-up considerations the following recommendations should be considered when connecting the sd-14620 series converters: 1) the +5 vdc power supply input is on pin 18. for performance with the lowest amount of noise it is recommended that a 10 f/10 vdc (or larger) tantalum filter capacitor be connect- ed to ground (pin 19) near the converter package. 2) direct inputs are referenced to analog ground (a gnd). connections should made as close to the converter package as possible to minimize noise. channel a should be refer- enced to a gnd-a (pin 5) and channel b should be refer- enced to a gnd-b (pin 32). 3) a 47 f/10 v tantalum filter capacitor must be added exter- nally from pin 52 (channel ? a ? filter point) to pin 19 (ground). in addition, a 47 f/10 vdc tantalum filter capacitor must be added externally from pin 24 (channel ? b ? filter point) to pin 19 (ground). special functions programmable resolution resolution is controlled by pins 49 and 50 for channel a; pins 21 and 22 for channel b. the resolution can be changed during con- verter operation, so the appropriate resolution and velocity dynamics can be changed as needed. to insure that a race con- dition does not exist between counting and changing the resolu- tion, the resolution control is latched internally. refer to table 2 for channel a and b resolution control. bit, (built-in-test) this output is an active low logic line that will flag an internal fault condition or los (loss-of-signal). the internal fault detector note: hbe enables the msb byte and lbe enables the lsb byte. 10800 5400 2700 1350 675 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 180 90 45 22.5 11.25 5.625 2.813 1.406 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 1 (msb all modes) 2 3 4 5 6 7 8 9 10 (lsb 10-bit mode) 11 12 (lsb 12-bit mode) 13 14 (lsb 14-bit mode) 15 16 (lsb 16-bit mode) min/bit deg/bit bit table 3. digital angle outputs
4 100 ns max em or el 150 ns max data data valid high z high z data data valid 500 ns max inhibit figure 2. connections for voltage transient suppressors figure 4. enable timing figure 3. inhibit timing rh rl 115 v ref. input cr1 cr3 cr2 for 90 v synchro inputs 90 v synchro input s1 hybrid s3 s2 cr1, cr2, and cr3 are 1.5ke170ca, bipolar transient voltage supressors or equivalent. cr4 is a 1.5ke200c. s1 s3 s2 cr4 monitors the internal loop error and, when it exceeds approximate- ly 100 lsbs, will set the line to a logic 0. this condition will occur during a large-step input and will reset to a logic 1 after the con- verter settles out. (the bit is filtered with a 500 s delay.) bit will set for an overvelocity condition because the converter loop can not maintain input/output sync. for the ? s ? option only, this output will be active low for a lor (loss-of-reference) fault condition. no false 180 hangup the converter is designed to eliminate a ? false 180 reading ? dur- ing instantaneous 180 step changes. this condition most often occurs when the input is ? electronically switched ? from a digital- to-synchro converter. if the ? msb ? (or 180 bit) is ? toggled ? on and off, a converter without the ? false 180 hangup ? feature may fail to respond. the condition is artificial, as a ? real ? synchro or resolver cannot change its output 180 instantaneously. the con- dition is most often noticed during wraparound verification tests, simulations, or troubleshooting. synthesized reference the synthesized reference section ( ? s ? option) eliminates errors due to phase shift between the reference and signal inputs. quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. due to the inductive nature of synchros and resolvers, their output signals lead the reference input signal (rh and rl). when an uncompensated reference signal is used to demodulate the control transformer ? s output, quadrature voltages are not completely eliminated. as shown in figure 1, the con- verter synthesizes its own internal reference signal based on the sin and cos signal inputs. therefore, the phase of the synthe- sized (internal) reference is determined by the signal input, result- ing in reduced quadrature errors. the synthesized reference cir- cuit also eliminates the 180 degree false error null hang up. interfacing solid-state buffer protection - transient voltage suppression the solid-state signal and reference inputs are true differential inputs with high ac and dc common rejection, so most applica- tions will not require units with isolation transformers. input imped- ance is maintained with power off. the recurrent ac peak + dc common-mode voltage should not exceed the values in table 1. the 90 v line-to-line systems may have voltage transients which exceed the 300 v specification listed in table 1. these tran- sients can destroy the thin-film input resistor network in the hybrid. therefore, 90 v l-l solid-state input modules may be protected by installing voltage suppressors (see figure 2). voltage transients are likely to occur whenever a synchro is switched on and off. for instance, a 1000 v transient can be gen- erated when the primary of a cx or tx input is opened. inhibit and enable timing the inhibit (inh ) signal is used to freeze the digital output angle in the transparent output data latch while the data is being trans- ferred. application of an inhibit signal does not interfere with the continuous tracking of the converter. as shown in figure 3, angular output data is valid 500 nanoseconds (maximum) after the application of the low-going inhibit pulse. output angle data is enabled onto the tri-state data bus in four bytes. this enable msb (em -a or em -b) is used for the most sig- nificant 8 bits and enable lsb (el -a or el -b) is used for the least significant bits. as shown in figure 4, output data is valid 150 nanoseconds (maximum) after the application of a low-going
5 -12 db/oct gain = 4 ba 2a -6 db/oct 10b (rad/sec) 2a 2 2 a (rad/sec) f = bw = 3db 2 a (hz) closed loop open loop - gain = 0.4 (b=a/2) (critically damped) figure 6. bode plots error processor input ( ) velocity out digital position out ( ) vco ct s a + 1 1 b s s + 1 10b h = 1 + - e a 2 s 2 s a +1 ( ) b 2 s s +1 ( ) 10b open loop transfer function = where: 2 a = a a 1 2 figure 5. transfer function block diagram enable pulse. the tri-state data bus returns to the high imped- ance state 100 nanoseconds (maximum) after the rising edge of the enable signal. dynamic performance a type ii servo loop (kv = ) and very high acceleration con- stants give the sd-14620 superior dynamic performance. transfer function and bode plot the dynamic performance of the converter can be determined from its functional block diagram (figure 1), its transfer func- tion block diagram (figure 5), and its bode plots (open and closed loop - figure 6). values for the transfer function block can be obtained from table 4. the open loop transfer function is as follows: where a is the gain coefficient and b is the frequency of lead compensation accuracy and resolution table 5 lists the total accuracy including quantification of the various resolutions and accuracy grades. 2 s a +1 ( ) b 2 s s +1 ( ) 10b open loop transfer function = table 4. dynamic characteristics device type 60 hz ? s ? option each channel input frequency bandwidth (closed loop) ka a1 a2 a b hz hz 1/s 2 1/s 1/s 1/s 1/s 47 - 5k 15 830 0.17 5k 29 14.5 1k - 5k 150 110k 2.47 44.4k 333 166 resolution bits 16 14 12 10 16 14 12 10 tracking rate (rps) typical minimum acceleration ( 1 lsb lag) settling time (179 step max) rps rps deg/s 2 msec 0.5 0.4 11.3 2500 2 1.6 45 1100 8 6.4 180 500 32 25.6 720 400 2.5 2 610 232 10 8 2440 150 40 32 9760 78 160 128 39k 51 400 hz 360 - 5k 56 53k 0.41 41k 130 81 16 14 12 10 2.5 2 93 360 10 8 372 180 40 32 1490 100 160 128 5950 90 table 5. accuracy/resolution version resolution (minutes) 10 bit 12 bit 14 bit 16 bit sd-1462x-xx accuracy (minutes) 4 +1 lsb 2 +1 lsb 42.2 42.2 10.5 10.5 5.3 3.3 4.3 2.3 sd-1462x-xs ( ? s ? option) * 1.3 minute accuracy available for ? s ? option only. inclusive of 1 bit of jitter. 4 +1 lsb 2 +1 lsb 1 +1 lsb 25.1 23.1 22.1 9.3 7.3 6.3 5.3 3.3 2.3 4.3 2.3 * 1.3
6 function pin pin function s1-b(s) n.c. s2-b(s) cos-b(d) s3-b(s) sin-b(d) n.c. n.c. s4-b(r) 31 filter point - channel b em-b (enable msbs chan. b) 37 24 a gnd-b (analog gnd. chan. b) +5 v (power supply) 18 bit-b (built-in-test chan. b) 38 32 inh-b (inhibit - chan. b) bit 12 (lsb, 12-bit mode) 17 bit 5 39 23 n.c. bit 4 16 bit 13 40 33 resolution control b (channel b) bit 11 15 bit 6 41 22 s2-b(r) bit 3 14 bit 14 (lsb, 14-bit mode) 42 29 vel b (velocity - chan. b) bit 10 (lsb, 10-bit mode) 13 bit 7 43 26 s1-b(r) bit 2 12 bit 15 44 28 n.c. bit 9 11 bit 8 45 27 s3-b(r) bit 1 (msb) 10 bit 16 (lsb, 16-bit mode) 46 30 e (dc error - channel b) bit-a (built-in-test chan. a) 9 n.c. 47 25 rl-b (-ref. input chan. b) em-a (enable msbs chan. a) 8 el-a (enable lsbs chan. a) 48 35 el-b (enable lsbs chan. b) rl-a (-ref. input chan. a) 7 resolution control a (chan. a) 49 20 rh-b (+ref. input chan. b) rh-a (+ref. input chan. a) 6 resolution control b (chan. a) 50 34 resolution control a (channel b) a gnd-a (analog gnd. chan. a) 5 inh-a (inhibit chan. a) 51 n.c. n.c. s4-a(r) 4 filter point - channel a 52 +sin-a(d) s3-a(s) s3-a(r) 3 e (dc error - channel a) 53 +cos-a(d) s2-a(s) s2-a(r) 2 vel a (velocity - chan. a) 54 n.c. s1-a(s) s1-a(r) 1 21 n.c. 36 gnd (ground) 19 table 6. pinouts (dip and flat pack) 0.780 max (19.81) 0.400 (10.16) 1.300 (33.02) index denotes pin 1 0.210 max (5.33) 1.500 max (36.75) 1.200 (30.48) 0.160 min (4.06) 0.050 (1.27) 0.100 typ (2.54) 0.050 typ (1.27) 0.600 (15.24) 0.018 dia typ (0.46) 26 27 28 29 53 54 2 1 3 52 30 25 numbers for reference only 0.008 (0.20) 0.05 (1.27) bottom view side view notes: 1. dimensions are in inches (mm). 2. lead identification numbers are for reference only 3. lead cluster shall be centered within 0.005 (0.13) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements to mil-std-202e, method 208c. 5. case is hermetically sealed ceramic package. figure 7. sd-14620 dip mechanical outline 26 eq. sp. @ 0.050 = 1.30 tol noncom typ (1.24 = 33.02) see note 2 0.500 min typ (12.7) 0.100 0.010 typ (2.54 0.25) 0.210 max (5.33) 28 27 54 1 0.780 max (19.81) pin 1 denoted by index mark 1.500 max (38.1) 0.010 0.002 typ (0.25 0.05) pin numbers for reference only 0.018 0.002 typ (0.46 0.05) 0.050 typ (1.27) 0.020 r typ (0.51) bottom view side view notes: 1. dimensions are in inches (mm). 2. lead cluster shall be centralized about case centerline within 0.010 (0.254). figure 8. sd-14620 flat pack mechanical outline notes: 1. (s) = synchro; (r) = resolver; (d) = 2 v resolver direct. 2. connect a 47 f/10 vdc tantalum filter cap from pins 24 to pin 19. 3. connect a 47 f/10 vdc tantalum filter cap from pin 52 to pin 19. 4. connect a 10 f/10 vdc tantalum filter cap from pin 18 to pin 19.
7 standard ddc processing test mil-std-883 method(s) condition(s) inspection 2009, 2010, 2017, and 2032 ? seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 a burn-in 1015, table 1 ? ordering information sd-1462x x x - x x x x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and pre-cap source y = one lot date code and 100% pull test z = one lot date code, pre-cap source and 100% pull test blank = none of the above accuracy: 2 = 4 min + 1 lsb 4 = 2 min + 1 lsb 5 = 1 min + 1 lsb (available with ?s? option only) reliability grade: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c + variables test data 5 = -40c to +85c + variables test data 8 = 0c to +70c + variables test data options: x = none s = synthesized reference package type: d = dip f = flat pack input options: 0 = 11.8 v, synchro, 400 hz 1 = 11.8 v, resolver, 400 hz 2 = 90 v, synchro, 400 hz 3 = 2 v, direct, 400 hz 4 = 90 v, synchro, 60 hz input options (?s? option): 1 = 11.8 v, resolver, 1 khz 3 = 2 v, resolver (differential), 1 khz *standard ddc processing with burn-in and full temperature test ? see table below.
8 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. h1-06/00-0 printed in the u.s.a. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7402 or 7413 headquarters - tel: (631) 567-5600 ext. 7402 or 7413, fax: (631) 567-7358 west coast - tel: (714) 895-9777, fax: (714) 895-4988 southeast - tel: (703) 450-7900, fax: (703) 450-6610 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 sweden - tel: +46-(0)8-54490044, fax +46-(0)8-7550570 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u
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